1. Field of the Invention
The present invention relates to a photolithography exposure process. More particularly, the present invention relates to method for determining focus and leveling of a chip.
2. Description of the Related Art
Photolithography is one of the important technologies for fabricating integrated circuits. For example, patterns of a variety of semiconductor layers are defined by photolithography. Thus, photolithography is a critical factor when semiconductor devices are downsized.
In an exposure technique of a photolithography process, depth of focus (DOF) and leveling of a chip are the key parameters that determine whether or not the pattern can be precisely transferred. Thus, during an exposure process, both depth of focus and leveling of different shots in the chip need to be considered, so as to entirely and precisely transfer patterns onto a photoresist layer on the chip.
In FIG. 1, a chip 10 comprises latitudinal scribe lines 20 and longitudinal scribe lines 22. The latitudinal scribe lines 20 and the longitudinal scribe lines 22 divide the chip 10 into dies 24. Since an exposure process is performed by a step and repeat process, the chip 10 needs to be divided into shots 14 in accord with an exposure area that a stepper is able to expose every time. Before the exposure process, an alignment mark 12 of each shot 14 is aligned with a mask alignment mark on a mark. Sensors are used to detect a focus and determine a focal plane of each shot 14, shot by shot. Each shot is leveled with the data obtained from the sensors. The exposure process thus is performed, shot by shot.
During detection, the sensor detects shots 14 with fixed detection points, shot by shot. As shown in FIG. 1, the detection points X, Y, and Z determine the focal plane of the shot 14. The shots 14 are divided into whole fields 14a and wafer edge fields 14b, which also known as non-whole fields. Each whole field 14a includes dies 24 that are complete squares, whereas each wafer edge field 14b includes at least one die 24 that is not complete square. Since the whole field 14a comprises the detection points X, Y, and Z, the focal plane of the whole field 14a is effectively determined. However, it is difficult for all three detection points X, Y and Z to fall on some of the wafer edge fields 14b. Since all the detection points X, Y, Z cannot fall on some of the wafer edge fields 14b, the conventional method has difficulties in detecting the wafer edge fields 14b with detection points X, Y, and Z. Therefore, an approximate heterodyne algorithm is used to estimate the focal plane of the wafer edge fields 14b.
However, during the fabrication of the chip 10, stress is generated and accumulated in the chip 10. This, in turn, causes the chip 10 to warp and deform. Reference is made to FIG. 2, which illustrates the reverse side of the deformed chip 10. The gradients of the whole fields 14a and the wafer edge fields 14b are particularly different. For example, in order to determine a focal plane the wafer edge field 14b, two whole fields nearby are selected. The detected focal planes A and B obtained from the whole fields 14a are used in the heterodyne algorithm to estimate the focal plane of the wafer edge field 14b. The estimated focal plane of the wafer edge field 14b falls at the focal plane D. However, the estimated focal plane D is different from the actual focal plane C. Since the estimated focal plane D is different from the actual focal plane C, while focal plane D serves as the focal plane of the wafer edge field 14b, the focus and the leveling are not optimal. Thus, patterns of the mask cannot be precisely transfer onto the chip 10. The fabrication yield is reduced.